1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including a plurality of semiconductor chips electrically connected by through silicon vias.
2. Description of Related Art
A memory capacity required in semiconductor memory devices such as DRAM (Dynamic Random Access Memory) is increasing every year. In recent years, there has been proposed a method to meet this requirement. In this method, a plurality of memory chips are stacked and electrically connected via through silicon vias arranged on a silicon substrate (see Japanese Patent Application Laid-open No. 2007-158237).
Specifically, in a semiconductor memory device in which an interface chip having front end units such as interface circuits incorporated thereon and a core chip having back end units such as memory cores incorporated thereon are stacked, because read data that is read in parallel from the memory cores is supplied as it is to the interface chip without performing serial conversion, a large number of through silicon vias (approximately 4000 units in some cases) are required. However, the entire chip becomes defective when even one of the through silicon vias becomes defective, and if a plurality of the chips are stacked, all the chips become defective. Thus, to prevent the entire chip from becoming defective due to a defective through silicon via, auxiliary through silicon vias are sometimes provided in such semiconductor memory devices.
In the semiconductor device disclosed in Japanese Patent Application Laid-open No. 2007-158237, one auxiliary through silicon via is allocated to a group of through silicon vias constituted by a plurality of through silicon vias (for example, eight through silicon vias).
If a defect occurs in one of the through silicon vias belonging to the group, the defective through silicon via is relieved by the auxiliary through silicon via allocated to the group.
As the number of stacked semiconductor chips increases, load on the through silicon vias also increases, and this may cause degradation in signal quality. Examinations performed by the inventor to find out a solution to this issue have proved that driver circuits (buffers) need to be provided to amplify signals, respectively, on an inlet and an outlet of the through silicon via. For example, there is assumed a state where signals are transmitted from an interface chip to a core chip via a through silicon via. If the signals are amplified by the driver circuit, provided on the interface chip side, immediately before the signals enter into the through silicon via, and the signals are re-amplified by the driver circuit, provided on the core chip side, immediately after the signals come out from the through silicon via, it becomes easy to maintain a good signal quality.
As described above, due to auxiliary through silicon vias, the interface chip can selectively use one through silicon via among the multiple through silicon vias. Therefore, a switch is necessary to select one path among a plurality of paths that connect a signal transmitting unit to each of the through silicon vias. Similarly, on the core chip side, a switch is necessary to select one path among a plurality of paths that connect each of the through silicon vias to a signal receiving unit. Normally, these switches are formed by transistors and they cause signal transmission delay. Because it is necessary to provide two switches in a path connecting the transmitting unit to the receiving unit via the through silicon via, signal delay tends to increase.
This problem is not limited to semiconductor memory devices such as DRAMs, but can occur to all semiconductor devices including semiconductor chips that are electrically connected to each other via through silicon vias.